Debug SystemVerilog testbench failures in the SVC project. Use when a testbench fails (make <module>_tb), to analyze CHECK_* assertion failures, watchdog timeouts, or unexpected signal values. Provides systematic debugging workflow using VCD waveforms and failure output analysis.
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TopRank Skills install pbozeman/debug-tb
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Skill Details
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Created
Jan 2026
Last Updated
6 months ago
tools
tools testing
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