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generate-4-bit-alu-in-vhdl

maintained by ECNU-ICALK

star 57 account_tree 5 verified_user MIT License
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Overview Implementation Examples History

Generates VHDL code for a 4-bit Arithmetic Logic Unit (ALU) with addition, subtraction, AND, OR, NOT operations and an unsupported flag, based on a specified entity and architecture structure.

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Skill Details

GitHub Stars 57
GitHub Forks 5
Created Mar 2026
Last Updated 3个月前
tools tools ide plugins

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